SN8P1602B
8-Bit Micro-Controller
MULTI-INTERRUPT OPERATION
Under certain condition, the software designer uses more than one interrupt requests. Processing multi-interrupt
request requires setting the priority of the interrupt requests. The IRQ flags of interrupts are controlled by the interrupt
event. Nevertheless, the IRQ flag “1” doesn’t mean the system will execute the interrupt vector. And which means the
IRQ flags can be set “1” by the events without enable the interrupt. Once the event occurs, the IRQ will be logic “1”.
The IRQ and its trigger event relationship is as the below table.
Interrupt Name
P00IRQ
Trigger Event Description
P0.0 trigger controlled by PEDGE
TC0C overflow
TC0IRQ
For multi-interrupt conditions, two things need to be taking care of. One is to set the priority for these interrupt requests.
Two is using IEN and IRQ flags to decide which interrupt to be executed. Users have to check interrupt control bit and
interrupt request flag in interrupt routine.
ꢁ
Example: Check the interrupt request under multi-interrupt operation
ORG
8
; Interrupt vector
B0XCH
B0MOV
B0MOV
A, ACCBUF
A, PFLAG
PFLAGBUF,A
; Store ACC value.
; Store PFLAG value
INTP00CHK:
INTTC0CHK:
INT_EXIT:
; Check INT0 interrupt request
; Check P00IEN
; Jump check to next interrupt
; Check P00IRQ
; Jump to INT0 interrupt service routine
; Check TC0 interrupt request
; Check TC0IEN
; Jump to exit of IRQ
; Check TC0IRQ
; Jump to TC0 interrupt service routine
B0BTS1
JMP
B0BTS0
JMP
FP00IEN
INTTC0CHK
FP00IRQ
INTP00
B0BTS1
JMP
B0BTS0
JMP
FTC0IEN
INT_EXIT
FTC0IRQ
INTTC0
B0MOV
B0MOV
B0XCH
A, PFLAGBUF
PFLAG,A
A, ACCBUF
; Restore PFLAG value
; Restore ACC value.
; Exit interrupt vector
RETI
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