SN8F2250B Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
6.10 TC1 INTERRUPT OPERATION
When the TC1C counter overflows, the TC1IRQ will be set to “1” no matter the TC1IEN is enable or disable. If the
TC1IEN and the trigger event TC1IRQ is set to be “1”. As the result, the system will execute the interrupt vector. If the
TC1IEN = 0, the trigger event TC1IRQ is still set to be “1”. Moreover, the system won’t execute interrupt vector even
when the TC1IEN is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation.
¾
Example: TC1 interrupt request setup.
B0BCLR
B0BCLR
MOV
B0MOV
MOV
FTC1IEN
FTC1ENB
A, #20H
TC1M, A
A, #74H
TC1C, A
; Disable TC1 interrupt service
; Disable TC1 timer
;
; Set TC1 clock = Fcpu / 64
; Set TC1C initial value = 74H
; Set TC1 interval = 10 ms
B0MOV
B0BSET
B0BCLR
B0BSET
FTC1IEN
FTC1IRQ
FTC1ENB
; Enable TC1 interrupt service
; Clear TC1 interrupt request flag
; Enable TC1 timer
B0BSET
FGIE
; Enable GIE
¾
Example: TC1 interrupt service routine.
ORG
JMP
8
; Interrupt vector
INT_SERVICE
INT_SERVICE:
…
; Push routine to save ACC and PFLAG to buffers.
B0BTS1
JMP
FTC1IRQ
EXIT_INT
; Check TC1IRQ
; TC1IRQ = 0, exit interrupt vector
B0BCLR
MOV
B0MOV
…
FTC1IRQ
A, #74H
TC1C, A
; Reset TC1IRQ
; Reset TC1C.
; TC1 interrupt service routine
…
EXIT_INT:
…
; Pop routine to load ACC and PFLAG from buffers.
; Exit interrupt vector
RETI
SONiX TECHNOLOGY CO., LTD
Page 65
Version 1.1
SONIX [ SONIX TECHNOLOGY COMPANY ]
