SN8P1700
8-bit micro-controller build-in 12-bit ADC
SN8P1706/SN8P1707/SN8P1708
0
L
1
H
2
R
3
Z
4
Y
5
X
6
7
8
-
9
-
A
-
B
-
C
-
D
-
E
-
F
-
PFLAG RBANK
8
9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
A
B
C
D
E
F
DAM
P1W
P0
-
ADM
P1M
P1
-
ADB
P2M
P2
-
ADR
SIOM
P4M
P4
-
SIOR
P5M
P5
-
SIOB
-
-
-
-
-
-
-
-
-
-
-
-
-
INTRQ INTEN OSCM
-
-
TC0R
PCL
PCH
T0M
-
T0C
-
TC0M TC0C TC1M TC1C TC1R STKP
@HL
@YZ
-
-
-
-
-
-
STK7L STK7H STK6L STK6H STK5L STK5H STK4L STK4H STK3L STK3H STK2L STK2H STK1L STK1H STK0L STK0H
Table 5-3. System Register Arrangement of SN8P1706/SN8P1707/SN8P1708
Description
L, H = Working & @HL addressing register.
R = Working register and ROM lookup data buffer.
Y, Z = Working, @YZ and ROM addressing register.
RBANK = RAM Bank Select register.
ADM = ADC’s mode register.
X = Working and ROM address register.
PFLAG = ROM page and special flag register.
DAM = DAC’s mode register.
ADB = ADC’s data buffer.
SIOM = SIO mode control register.
SIOB = SIO’s data buffer.
ADR = ADC’s resolution selects register.
SIOR = SIO’s clock reload buffer.
P1W = Port 1 wakeup register.
PnM = Port n input/output mode register.
INTRQ = Interrupts’ request register.
OSCM = Oscillator mode register.
T0M = Timer 0 mode register.
Pn = Port n data buffer.
INTEN = Interrupts’ enable register.
PCH, PCL = Program counter.
TC0M = Timer/Counter 0 mode register.
TC0C = Timer/Counter 0 counting register.
TC0R = Timer/Counter 0 auto-reload data buffer.
TC1R = Timer/Counter 1 auto-reload data buffer.
STK0~STK7 = Stack 0 ~ stack 7 buffer.
@YZ = RAM YZ indirect addressing index pointer.
T0C = Timer 0 counting register.
TC1M = Timer/Counter 1 mode register.
TC1C = Timer/Counter 1 counting register.
STKP = Stack pointer buffer.
@HL = RAM HL indirect addressing index pointer.
ꢂ
Note:
a). All of register names had been declared in SONiX 8-bit MCU assembler.
b). One-bit name had been declared in SONiX 8-bit MCU assembler with “F” prefix code.
c). It will get logic “H” data, when use instruction to check empty location.
d). The low nibble of ADR register is read only.
e). “b0bset”, “b0bclr”, ”bset”, ”bclr” instructions only support “R/W” registers.
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