SN8P1700
8-bit micro-controller build-in 12-bit ADC
FALLING EDGE RECEIVER MODE
ꢃExample: Master Rx falling edge
MOV
B0MOV
MOV
B0MOV
B0BSET
A,#0FFH
SIOR,A
A,#10000000B
SIOM,A
; Set SIO clock with auto-reload function.
; Setup SIOM and enable SIO function. Falling edge.
; Start receiving SIO data.
FSTART
CHK_END:
B0BTS0
JMP
B0MOV
MOV
FSTART
CHK_END
A,SIOB
; Wait the end of SIO operation.
; Save SIOB data into RXDATA buffer.
RXDATA,A
RX data
SCK
SI
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
LSB
MSB
SO
Normal I/O Application
Figure 10-7. The Falling Edge Timing Diagram of Master Receiving Operation
SONiX TECHNOLOGY CO., LTD
Page 107
Revision 1.94
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