SN8P1700
8-bit micro-controller build-in 12-bit ADC
Figure 9-2 shows a typical transfer between two microcontrollers. Process 1 sends SCK for initial the data transfer.
Both processors must work in the same clock edge direction, then both controllers would send and receive data at the
same time.
SDI
SDO
SIOM Register
SIOM Register
SDO
SCK
SDI
SIOB 8 Bit Buffer
SIOB 8 Bit Buffer
MSB
LSB
MSB
LSB
SIO Clock
SCK
PROCESS 1
PROCESS 2
Figure 10-2. SIO Data Transfer Diagram
SIOM MODE REGISTER
SIOM initial value = 0000 x000
0B4H
SIOM
Bit 7
SENB
R/W
Bit 6
START
R/W
Bit 5
SRATE1
R/W
Bit 4
SRATE0
R/W
Bit 3
0
-
Bit 2
SCKMD
R/W
Bit 1
SEDGE
R/W
Bit 0
TXRX
R/W
SENB: SIO function control bit. 0 = disable (P5.0~P5.2 is general purpose port), 1 = enable (P5.0~P5.2 is SIO
pins).
START: SIO progress control bit. 0 = End of transfer, 1 = progressing.
SRATE1, 0: SIO’s transfer rate select bit. 00 = fcpu, 01 = fcpu/32, 10 = fcpu/16, 11 = fcpu/8.
(Note: These 2-bits are workless when SCKMD=1)
SCKMD: SIO’s clock mode select bit. 0 = internal, 1 = external mode.
SEDGE: SIO’s transfer clock edge select bit. 0 = falling edge, 1 = raising edge.
TXRX: SIO’s transfer direction select bit. 0 = receiver only , 1 = transmitter/receiver full duplex.
ꢂ
ꢂ
Note 1: If SCKMD=1 for external clock, the SIO is in SLAVE mode.
If SCKMD=0 for internal clock, the SIO is in MASTER mode.
Note 2: Don’t set SENB and START bits in the same time. That makes the SIO function error.
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