SN8P1700
8-bit micro-controller build-in 12-bit ADC
8TIMERS COUNTERS
WATCHDOG TIMER (WDT)
The watchdog timer (WDT) is a binary up counter designed for monitoring program execution. If the program get into
the unknown status by noise interference, WDT’s overflow signal will reset this chip and restart operation. The
instruction that clear the watch-dog timer (B0BSET FWDRST) should be executed at proper points in a program
within a given period. If an instruction that clears the watchdog timer is not executed within the period and the
watchdog timer overflows, reset signal is generated and system is restarted with reset status. In order to generate
different output timings, the user can control watchdog timer by modifying Wdrate control bits of OSCM register. The
watchdog timer will be disabled at green and power down modes.
OSCM initial value = 0000 000x
0CAH
OSCM
Bit 7
0
-
Bit 6
WDRST
R/W
Bit 5
Wdrate
R/W
Bit 4
-
-
Bit 3
CPUM0
R/W
Bit 2
CLKMD
R/W
Bit 1
STPHX
R/W
Bit 0
-
-
ꢂ
Notice: The bit 7 must be “0”, or the system will be error.
Wdrate: Watchdog timer rate select bit. 0 =14th, 1 = 8th.
WDRST : Watch dog timer reset bit. 0 = Non reset, 1 = clear the watchdog timer’s counter.
Watchdog timer overflow time
Wdrate
External high-speed oscillator
1 / ( fcpu ÷ 214 ÷ 16 ) = 293 ms, Fosc=3.58MHz
0
1 / ( fcpu ÷ 214 ÷ 16 ) = 32 s, Fosc=32768Hz
1 / ( fcpu ÷ 28 ÷ 16 ) = 4.5 ms, Fosc=3.58MHz
1
1 / ( fcpu ÷ 28 ÷ 16 ) = 500 ms, Fosc=32768Hz
Figure 8-1. Watchdog timer overflow time table
ꢂ
Note: The watch dog timer can be enabled or disabled by the code option.
ꢃExample: An operation of watch-dog timer is as following. To clear the watchdog timer’s counter in the top
of the main routine of the program.
Main:
B0BSET
FWDRST
; Clear the watchdog timer’s counter.
.
.
CALL
SUB1
CALL
SUB2
.
.
.
.
.
.
JMP
MAIN
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