SN8P1700
8-bit micro-controller build-in 12-bit ADC
ADM REGISTER
ADM initial value = 0000 x000
0B1H
ADM
Bit 7
ADENB
R/W
Bit 6
ADS
R/W
Bit 5
EOC
R/W
Bit 4
GCHS
R/W
Bit 3
-
-
Bit 2
CHS2
R/W
Bit 1
CHS1
R/W
Bit 0
CHS0
R/W
CHS2, 1, 0: ADC input channels select bit. 000 = AIN0, 001 = AIN1, 010 = AIN2, 011 = AIN3, .. , 111 = AIN7.
GCHS: Global channel select bit. 0 = To disable AIN channel, 1 = To enable AIN channel.
EOC: ADC status bit. 0 = Progressing, 1 = End of converting and reset ADENB bit.
ADS: ADC start bit. 0 = stop, 1 = starting.
ADENB: ADC control bit. 0 = disable, 1 = enable.
ADR REGISTERS
ADR initial value = x00x 0000
0B3H
ADR
Bit 7
-
-
Bit 6
ADCKS
R/W
Bit 5
ADLEN
R/W
Bit 4
0
-
Bit 3
ADB3
R
Bit 2
ADB2
R
Bit 1
ADB1
R
Bit 0
ADB0
R
ADBn: ADC data buffer. ADB11~ADB4 bits for 8-bit ADC. ADB11~ADB0 bits for 12-bit ADC.
ADLEN: ADC’s resolution select bits. 0 = 8-bit, 1 = 12-bit.
ADCKS: ADC’s clock source select bit.
ADCKS ADC clock source Note
0
1
Fcpu/4
Fhosc
Both validate in Normal mode and Slow mode
Only validate in Normal mode
ADB REGISTERS
ADB initial value = xxxx xxxx
0B2H
ADB
Bit 7
ADB11
R
Bit 6
ADB10
R
Bit 5
ADB9
R
Bit 4
ADB8
R
Bit 3
ADB7
R
Bit 2
ADB6
R
Bit 1
ADB5
R
Bit 0
ADB4
R
ADB is ADC data buffer to store AD converter result. The ADB is only 8-bit register including bit 4~bit11 ADC data. To
combine ADB register and the low-nibble of ADR will get full 12-bit ADC data buffer. The ADC buffer is a read-only
register. In 8-bit ADC mode, the ADC data is stored in ADB register. In 12-bit ADC mode, the ADC data is stored in
ADB and ADR registers.
SONiX TECHNOLOGY CO., LTD
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Revision 1.94
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