Preliminary
SN8P1702A/SN8P1703A
8-bit micro-controller build-in 12-bit ADC
ADM REGISTER
ADM initial value = 0000 x000
0B1H
ADM
Bit 7
ADENB
R/W
Bit 6
ADS
R/W
Bit 5
EOC
R/W
Bit 4
GCHS
R/W
Bit 3
-
-
Bit 2
-
-
Bit 1
CHS1
R/W
Bit 0
CHS0
R/W
Bit[1:0]
CHS[1:0]: ADC input channels select bit.
00 = AIN0
01 = AIN1
10 = AIN2
11 = AIN3
Bit4
Bit5
Bit6
Bit7
GCHS:Global channel select bit.
0 = to disable AIN channel
1 = to enable AIN channel.
EOC: ADC status bit.
0 = Progressing
1 = End of converting and reset ADENB bit.
ADS:ADC start bit.
0 = stop
1 = starting.
ADENB:ADC control bit.
0 = disable
1 = enable.
ADR REGISTERS
ADR initial value = x00x 0000
0B3H
ADR
Bit 7
-
-
Bit 6
ADCKS1
R/W
Bit 5
ADLEN
R/W
Bit 4
ADCKS0
R/W
Bit 3
ADB3
R
Bit 2
ADB2
R
Bit 1
ADB1
R
Bit 0
ADB0
R
Bit[3:0]
ADBn: ADC data buffer.
ADB11~ADB4 data for 8-bit ADC.
ADB11~ADB0 data for 12-bit ADC.
ADLEN: ADC’s resolution select bits.
0 = 8-bit
Bit5
1 = 12-bit.
Bit6,Bit4 ADCKS1, ADCKS0: ADC’s clock source select bit.
ADCKS1 ADCKS0 ADC Clock Source Note
0
0
1
1
0
1
0
1
Fcpu/4
Fcpu/2
Fhosc
Both validate in Normal mode and Slow mode
Both validate in Normal mode and Slow mode
Only validate in Normal mode
Fhosc/2
Only validate in Normal mode
SONiX TECHNOLOGY CO., LTD
Page 95
Revision 0.5
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