Preliminary
OSCM REGISTER DESCRIPTION
SN8P1702A/SN8P1703A
8-bit micro-controller build-in 12-bit ADC
The OSCM register is a oscillator control register. It can control oscillator select, system mode, watchdog timer clock
source and rate.
OSCM initial value = 000x 000x
0CAH
OSCM
Bit 7
WTCKS
R/W
Bit 6
WDRST
R/W
Bit 5
Wdrate
R/W
Bit 4
CPUM1
R/W
Bit 3
CPUM0
R/W
Bit 2
CLKMD
R/W
Bit 1
STPHX
R/W
Bit 0
0
-
Bit1
Bit2
STPHX: External high-speed oscillator control bit.
0 = free run,
1 = stop.
Note: This bit only controls external high-speed oscillator. If STPHX=1, the internal low-speed RC
oscillator is still running.
ꢀ
CLKMD: System high/Low speed mode select bit.
0 = normal (dual) mode,
1 = slow mode.
Bit[4:3] CPUM[1:0]: CPU operating mode control bit.
00 = normal,
01 = sleep (power down) mode,
10 = green mode,
11 = reserved.
Bit5
Bit6
Bit7
Wdrate: Watchdog timer rate select bit.
0 = Fcpu ÷ 214
1 = Fcpu ÷ 28
(The detail information is in watchdog timer chapter.)
WDRST: Watchdog timer reset bit.
0 = Non reset,
1 = clear the watchdog timer’s counter.
(The detail information is in watchdog timer chapter.)
WTCKS: Watchdog clock source select bit.
0 = Fcpu,
1 = internal RC low clock.
SONiX TECHNOLOGY CO., LTD
Page 43
Revision 0.5
SONIX [ SONIX TECHNOLOGY COMPANY ]
