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SN8A1703AP 参数 Datasheet PDF下载

SN8A1703AP图片预览
型号: SN8A1703AP
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器 [8-Bit Micro-Controller]
分类和应用: 微控制器
文件页数/大小: 112 页 / 624 K
品牌: SONIX [ SONIX TECHNOLOGY COMPANY ]
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Preliminary  
SN8P1702A/SN8P1703A  
8-bit micro-controller build-in 12-bit ADC  
INTEN INTERRUPT ENABLE REGISTER  
INTEN is the interrupt request control register including two internal interrupts, one external interrupts enable control  
bits. One of the register to be set “1” is to enable the interrupt request function. Once of the interrupt occur, the  
program jump to ORG 8 to execute interrupt service routines. The program exits the interrupt service routine when the  
returning interrupt service routine instruction (RETI) is executed.  
INTEN initial value = x000 0000  
0C9H  
INTEN  
Bit 7  
0
-
Bit 6  
TC1IEN  
R/W  
Bit 5  
TC0IEN  
R/W  
Bit 4  
0
-
Bit 3  
0
-
Bit 2  
0
-
Bit 1  
0
-
Bit 0  
P00IEN  
R/W  
Bit0  
P00IEN:External P0.0 interrupt control bit.  
0 = disable,  
1 = enable.  
Bit5  
Bit6  
TC0IEN:Timer interrupt control bit.  
0 = disable,  
1 = enable.  
TC1IEN:Timer interrupt control bit.  
0 = disable,  
1 = enable.  
INTRQ INTERRUPT REQUEST REGISTER  
INTRQ is the interrupt request flag register. The register includes all interrupt request indication flags. Each one of  
these interrupt request occurs, the bit of the INTRQ register would be set “1”. The INTRQ value needs to be clear by  
programming after detecting the flag. In the interrupt vector of program, users know the any interrupt requests  
occurring by the register and do the routine corresponding of the interrupt request.  
INTRQ initial value = x000 0000  
0C8H  
INTRQ  
Bit 7  
0
-
Bit 6  
TC1IRQ  
R/W  
Bit 5  
TC0IRQ  
R/W  
Bit 4  
0
-
Bit 3  
0
-
Bit 2  
0
-
Bit 1  
0
-
Bit 0  
P00IRQ  
R/W  
Bit0  
P00IRQ:External P0.0 interrupt request bit.  
0 = non-request  
1 = request.  
Bit5  
Bit6  
TC0IRQ:TC0 timer interrupt request controls bit.  
0 = non request  
1 = request.  
TC1IRQ:TC1 timer interrupt request controls bit.  
0 = non request  
1 = request.  
When interrupt occurs, the related request bit of INTRQ register will be set to “1” no matter the related enable bit of  
INTEN register is enabled or disabled. If the related bit of INTEN = 1 and the related bit of INTRQ is also set to be “1”.  
As the result, the system will execute the interrupt vector (ORG 8). If the related bit of INTEN = 0, moreover, the  
system won’t execute interrupt vector even when the related bit of INTRQ is set to be “1”. Users need to be cautious  
with the operation under multi-interrupt situation.  
SONiX TECHNOLOGY CO., LTD  
Page 80  
Revision 0.5  
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