Preliminary
SN8P1702A/SN8P1703A
8-bit micro-controller build-in 12-bit ADC
8TIMERS COUNTERS
WATCHDOG TIMER (WDT)
The watchdog timer (WDT) is a binary up counter designed for monitoring program execution. If the program gets in
the unknown status by noise interference, The WDT’s overflow signal will reset this chip and restart operation. The
instruction that clear the watch-dog timer (B0BSET FWDRST) should be executed at proper points in a program
within a given period. If an instruction that clears the watchdog timer is not executed within the period and the
watchdog timer overflows, reset signal is generated and system is restarted with reset status. In order to generate
different output timings, the user can control watchdog timer by modifying the Wdrate control bits of OSCM register.
The watchdog timer will be disabled at green and power down modes.
OSCM initial value = 0000 000x
0CAH
OSCM
Bit 7
WTCKS
R/W
Bit 6
WDRST
R/W
Bit 5
Wdrate
R/W
Bit 4
CPUM1
R/W
Bit 3
CPUM0
R/W
Bit 2
CLKMD
R/W
Bit 1
STPHX
R/W
Bit 0
-
-
Bit1
Bit2
STPHX: External high-speed oscillator control bit.
0 = free run,
1 = stop.
Note: This bit only controls external high-speed oscillator. If STPHX=1, the internal low-speed RC
oscillator is still running.
CLKMD: System high/Low speed mode select bit.
0 = normal (dual) mode,
1 = slow mode.
Bit[4:3] CPUM[1:0]: CPU operating mode control bit.
00 = normal,
01 = sleep (power down) mode,
10 = green mode,
11 = reserved.
Bit5
Bit6
Wdrate: Watchdog timer rate select bit.
0 = Fcpu ÷ 214
1 = Fcpu ÷ 28
WDRST: Watchdog timer reset bit.
0 = Non reset,
1 = clear the watchdog timer’s counter.
(The detail information is in watchdog timer chapter.)
Bit7
WTCKS: Watchdog clock source select bit.
0 = Fcpu,
1 = internal RC low clock.
WTCKS WTRATE CLKMD
Watchdog Timer Overflow Time
1 / ( Fcpu ÷ 214 ÷ 16 ) = 293 ms, Fosc=3.58MHz
1 / ( Fcpu ÷ 28 ÷ 16 ) = 500 ms, Fosc=32768Hz
1 / ( Fcpu ÷ 214 ÷ 16 ) = 65.5s, Fosc=16KHz@3V
1 / ( Fcpu ÷ 28 ÷ 16 ) = 1s, Fosc=16KHz@3V
1 / ( 16K ÷ 512 ÷ 16 ) ~ 0.5s @3V
0
0
0
0
1
0
1
0
1
-
0
0
1
1
-
Table 8-1. Watchdog timer overflow timetable
SONiX TECHNOLOGY CO., LTD
Page 53
Revision 0.5
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