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SN8A1703AP 参数 Datasheet PDF下载

SN8A1703AP图片预览
型号: SN8A1703AP
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器 [8-Bit Micro-Controller]
分类和应用: 微控制器
文件页数/大小: 112 页 / 624 K
品牌: SONIX [ SONIX TECHNOLOGY COMPANY ]
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Preliminary  
SN8P1702A/SN8P1703A  
8-bit micro-controller build-in 12-bit ADC  
5SYSTEM REGISTER  
OVERVIEW  
The system special register is located at 80h~FFh. The main purpose of system registers is to control the peripheral  
hardware of the chip. Using system registers can control I/O ports, SIO, ADC, PWM, timers and counters by  
programming. The Memory map provides an easy and quick reference source for writing application program. To  
accessing these system registers is controlled by the select memory bank (RBANK = 0) or the bank 0 read/write  
instruction (B0MOV, B0BSET, B0BCLR…).  
SYSTEM REGISTER ARRANGEMENT (BANK 0)  
BYTES of SYSTEM REGISTER  
SN8P1702  
0
-
1
-
2
R
3
Z
4
Y
5
-
6
7
-
8
-
9
-
A
-
B
-
C
-
D
-
E
-
F
-
PFLAG  
8
9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P4CON  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
A
B
C
D
E
F
-
ADM  
P1M  
P1  
ADB  
ADR  
-
-
-
-
-
-
-
-
-
PEDGE  
PCH  
P1W  
P0  
-
-
P4M  
P4  
P5M  
P5  
-
-
INTRQ INTEN OSCM  
-
-
TC0R  
PCL  
-
-
-
-
-
-
-
T0M  
-
-
-
TC0M TC0C TC1M TC0C TC1R STKP  
P0UR P1UR  
STK7 STK7  
P4UR P5UR  
STK5 STK5  
@YZ  
STK4  
-
-
-
-
-
-
STK6  
STK6  
STK4  
STK3  
STK3  
STK2  
STK2  
STK1  
STK1  
STK0  
STK0  
Table 5-1. System Register Arrangement  
Description  
PFLAG = ROM page and special flag register.  
ADB = ADC’s data buffer.  
PnM = Port n input/output mode register.  
INTRQ = Interrupts’ request register.  
R = Working register and ROM lookup data buffer.  
Y, Z = Working, @YZ and ROM addressing register.  
RBANK = RAM Bank Select register.  
ADM = ADC’s mode register.  
OSCM = Oscillator mode register.  
ADR = ADC’s resolution selects register.  
P1W = Port 1 wakeup register.  
Pn = Port n data buffer.  
TC0/1M = Timer/Counter 0/1 mode register.  
TC0/1C = Timer/Counter 0/1 counting register.  
TC0/1R = Timer/Counter 0/1 auto-reload data buffer.  
STKP = Stack pointer buffer.  
PnUR= Pull-up register  
INTEN = Interrupts’ enable register.  
PCH, PCL = Program counter.  
@HL = RAM HL indirect addressing index pointer.  
STK0~STK7 = Stack 0 ~ stack 7 buffer.  
@YZ = RAM YZ indirect addressing index pointer.  
Note:  
a). All of register names had been declared in SONiX 8-bit MCU assembler.  
b). One-bit name had been declared in SONiX 8-bit MCU assembler with “F” prefix code.  
c). It will get logic “H” data, when use instruction to check empty location.  
d). The low nibble of ADR register is read only.  
e). “b0bset”, “b0bclr”, ”bset”, ”bclr” instructions only support “R/W” registers.  
SONiX TECHNOLOGY CO., LTD  
Page 37  
Revision 0.5  
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