SN8P1700
8-bit micro-controller build-in 12-bit ADC
15 INSTRUCTION SET TABLE
Field
Mnemonic
A,M
Description
C
-
-
DC
Z
√
-
Cycle
MOV
MOV
-
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
2
A ← M
M
O
V
E
M,A
M ← A
B0MOV
B0MOV
MOV
A,M
M,A
A,I
-
A ← M (bnak 0)
M (bank 0) ← A
A ← I
√
-
-
-
-
B0MOV
M,I
-
-
M ← I, (M = only for Working registers R, Y, Z , RBANK & PFLAG)
XCH
A,M
A,M
-
-
A ←→M
B0XCH
MOVC
-
-
A ←→M (bank 0)
R, A ← ROM [Y,Z]
-
-
ADC
ADC
ADD
ADD
B0ADD
ADD
SBC
A,M
M,A
A,M
M,A
M,A
A,I
1
1
1
1
1
1
1
1
1
1
1
1
2
A ← A + M + C, if occur carry, then C=1, else C=0
M ← A + M + C, if occur carry, then C=1, else C=0
A ← A + M, if occur carry, then C=1, else C=0
√
√
√
√
√
√
√
√
√
√
√
√
-
√
√
√
√
√
√
√
√
√
√
√
-
√
√
√
√
√
√
√
√
√
√
√
-
A
R
I
M ← A + M, if occur carry, then C=1, else C=0
T
H
M
E
T
I
M (bank 0) ← M (bank 0) + A, if occur carry, then C=1, else C=0
A ← A + I, if occur carry, then C=1, else C=0
A,M
M,A
A,M
M,A
A,I
A ← A - M - /C, if occur borrow, then C=0, else C=1
M ← A - M - /C, if occur borrow, then C=0, else C=1
A ← A - M, if occur borrow, then C=0, else C=1
SBC
SUB
SUB
M ← A - M, if occur borrow, then C=0, else C=1
C
SUB
DAA
MUL
A ← A - I, if occur borrow, then C=0, else C=1
To adjust ACC’s data format from HEX to DEC.
A,M
-
R, A ← A * M, The LB of product stored in Acc and HB stored in R register. ZF affected by Acc.
√
AND
AND
AND
OR
A,M
M,A
A,I
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
1
A ← A and M
M ← A and M
A ← A and I
A ← A or M
M ← A or M
A ← A or I
√
√
√
√
√
√
√
√
√
L
O
G
I
A,M
M,A
A,I
OR
C
OR
XOR
XOR
XOR
A,M
M,A
A,I
A ← A xor M
M ← A xor M
A ← A xor I
SWAP
SWAPM
RRC
M
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
1
1
1
A (b3~b0, b7~b4) ←M(b7~b4, b3~b0)
M(b3~b0, b7~b4) ← M(b7~b4, b3~b0)
A ← RRC M
P
R
O
C
E
S
M
M
√
√
√
√
-
RRCM
RLC
M
M ← RRC M
M
A ← RLC M
RLCM
CLR
M
M ← RLC M
M
M ← 0
S
BCLR
BSET
M.b
M.b
M.b
M.b
-
M.b ← 0
-
M.b ← 1
B0BCLR
B0BSET
-
M(bank 0).b ← 0
M(bank 0).b ← 1
-
CMPRS
CMPRS
INCS
A,I
A,M
M
-
-
-
-
-
-
-
-
-
-
-
-
1 + S
1 + S
1 + S
1 + S
1 + S
1 + S
1 + S
1 + S
1 + S
1 + S
2
ZF,C ← A - I, If A = I, then skip next instruction
ZF,C ← A – M, If A = M, then skip next instruction
A ← M + 1, If A = 0, then skip next instruction
M ← M + 1, If M = 0, then skip next instruction
A ← M - 1, If A = 0, then skip next instruction
M ← M - 1, If M = 0, then skip next instruction
If M.b = 0, then skip next instruction
√
√
-
√
√
-
B
R
A
N
C
H
INCMS
DECS
M
-
-
M
-
-
DECMS
BTS0
BTS1
B0BTS0
B0BTS1
JMP
M
-
-
-
-
-
-
-
-
-
-
-
-
M.b
M.b
M.b
M.b
d
If M.b = 1, then skip next instruction
If M(bank 0).b = 0, then skip next instruction
If M(bank 0).b = 1, then skip next instruction
PC15/14 ← RomPages1/0, PC13~PC0 ← d
Stack ← PC15~PC0, PC15/14 ← RomPages1/0, PC13~PC0 ← d
CALL
d
-
-
2
M
I
S
C
RET
-
-
-
√
-
-
-
-
-
√
-
-
-
-
-
√
-
√
2
2
1
1
1
-
PC ← Stack
RETI
PUSH
POP
PC ← Stack, and to enable global interrupt
To push working registers (080H~087H) into buffers
To pop working registers (080H~087H) from buffers
No operation
NOP
@SET_PUR VAL
Enable or disable pull-up resisters. Bit N of VAL: “0” disable port N pull-up, “1” enable port N pull-up
Table 15-1. Instruction Set Table of SN8P1700
Note 1: Any instruction that read/write from 0SCM, will add an extra cycle.)
Note 2: SN8P1702/SN8A1702 don’t provide “MUL, PUSH, POP” instruction.
SONiX TECHNOLOGY CO., LTD
Page 134
Revision 1.94
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