Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver
Datasheet
FIELD NAME
BIT
ACCESS
DEFAULT DESCRIPTION
000b Read only, 0.
Reserved
7:5
rd
7.1.1.10
USB Interrupt Status
Address = 13h (read only)
This register dynamically updates to reflect current status of interrupt sources.
FIELD NAME
BIT
ACCESS
DEFAULT DESCRIPTION
HostDisconnect
0
0b
Current value of the UTMI+ Hi-Speed Hostdisconnect
rd
output. Applicable only in host mode.
Current value of the UTMI+ Vbusvalid output.
Current value of the UTMI+ SessValid output.
Current value of the UTMI+ SessEnd output.
Current value of the UTMI+ IdGnd output.
Read only, 0.
VbusValid
SessValid
SessEnd
IdGnd
1
2
rd
rd
rd
rd
rd
0b
0b
3
0b
4
0b
Reserved
7:5
000b
Note: The default conditions will match the current status of the comparators. The values shown are
for an unattached OTG device.
7.1.1.11
USB Interrupt Latch
Address = 14h (read only with auto clear)
FIELD NAME
BIT
ACCESS
DEFAULT DESCRIPTION
HostDisconnect Latch
0
0b
Set to 1b by the transceiver when an unmasked
event occurs on Hostdisconnect. Cleared when this
register is read. Applicable only in host mode.
rd
(Note 7.2)
VbusValid Latch
SessValid Latch
SessEnd Latch
IdGnd Latch
1
2
0b
Set to 1b by the transceiver when an unmasked
event occurs on VbusValid. Cleared when this
register is read.
rd
(Note 7.2)
0b
Set to 1b by the transceiver when an unmasked
event occurs on SessValid. Cleared when this
register is read.
rd
(Note 7.2)
3
0b
Set to 1b by the transceiver when an unmasked
event occurs on SessEnd. Cleared when this register
is read.
rd
(Note 7.2)
4
0b
Set to 1b by the transceiver when an unmasked
event occurs on IdGnd. Cleared when this register is
read.
rd
(Note 7.2)
Reserved
7:5
rd
000b
Read only, 0.
Note 7.2 rd: Read Only with auto clear.
Revision 1.0 (07-14-09)
SMSC USB3320
DATA6S6HEET
SMSC [ SMSC CORPORATION ]
