Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver
Datasheet
FIELD NAME
BIT
ACCESS
DEFAULT DESCRIPTION
00h SMSC Product ID
Product ID High
7:0
rd
7.1.1.5
Function Control
Address = 04-06h (read), 04h (write), 05h (set), 06h (clear)
FIELD NAME
BIT
ACCESS
DEFAULT DESCRIPTION
XcvrSelect[1:0]
1:0
rd/w/s/c
01b
Selects the required transceiver speed.
00b: Enables HS transceiver
01b: Enables FS transceiver
10b: Enables LS transceiver
11b: Enables FS transceiver for LS packets (FS
preamble automatically pre-pended)
TermSelect
OpMode
2
rd/w/s/c
rd/w/s/c
0b
Controls the DP and DM termination depending on
XcvrSelect, OpMode, DpPulldown, and DmPulldown.
The DP and DM termination is detailed in Table 5.1.
4:3
00b
Selects the required bit encoding style during
transmit.
00b: Normal Operation
01b: Non-Driving
10b: Disable bit-stuff and NRZI encoding
11b: Reserved
Reset
5
6
7
rd/w/s/c
rd/w/s/c
rd
0b
1b
0b
Active high transceiver reset. This reset does not
reset the ULPI interface or register set. Automatically
clears after reset is complete.
SuspendM
Reserved
Active low PHY suspend. When cleared the
transceiver will enter Low Power Mode as detailed in
6.3. Automatically set when exiting Low Power Mode.
Read only, 0.
7.1.1.6
Interface Control
Address = 07-09h (read), 07h (write), 08h (set), 09h (clear)
FIELD NAME
BIT
ACCESS
DEFAULT DESCRIPTION
6-pin FsLsSerialMode
0
rd/w/s/c
0b
0b
0b
When asserted the ULPI interface is redefined to the
6-pin Serial Mode. The transceiver will automatically
clear this bit when exiting serial mode.
3-pin FsLsSerialMode
CarkitMode
1
2
rd/w/s/c
rd/w/s/c
When asserted the ULPI interface is redefined to the
3-pin Serial Mode. The transceiver will automatically
clear this bit when exiting serial mode.
When asserted the ULPI interface is redefined to the
Carkit interface. The transceiver will automatically
clear this bit when exiting Carkit Mode.
SMSC USB3320
Revision 1.0 (07-14-09)
DATA6S3HEET
SMSC [ SMSC CORPORATION ]
