Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver
Datasheet
Chapter 7 ULPI Register Map
7.1
ULPI Register Array
The USB3320 Transceiver implements all of the ULPI registers detailed in the ULPI revision 1.1
specification. The complete USB3320 ULPI register set is shown in Table 7.1. All registers are 8 bits.
This table also includes the default state of each register upon POR or de-assertion of RESETB, as
described in Section 5.5.2. The RESET bit in the Function Control Register does not reset the bits of
the ULPI register array. The Link should not read or write to any registers not listed in this table.
The USB3320 supports extended register access. The immediate register set (00-3Fh) can be
accessed through either a immediate address or an extended register address.
Table 7.1 ULPI Register Map
ADDRESS (6BIT)
DEFAULT
REGISTER NAME
STATE
READ
WRITE
SET
CLEAR
Vendor ID Low
24h
04h
07h
00h
41h
00h
06h
1Fh
1Fh
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
01h
-
-
-
-
-
-
Vendor ID High
Product ID Low
02h
-
-
-
Product ID High
Function Control
Interface Control
OTG Control
03h
-
-
-
04-06h
07-09h
0A-0Ch
0D-0Fh
10-12h
13h
04h
07h
0Ah
0Dh
10h
-
05h
08h
0Bh
0Eh
11h
-
06h
09h
0Ch
0Fh
12h
-
USB Interrupt Enable Rising
USB Interrupt Enable Falling
USB Interrupt Status (Note 7.1)
USB Interrupt Latch
Debug
14h
-
-
-
15h
-
-
-
Scratch Register
Carkit Control
16-18h
19-1Bh
16h
19h
17h
1Ah
18h
1Bh
Reserved
1Ch
Carkit Interrupt Enable
Carkit Interrupt Status
Carkit Interrupt Latch
Reserved
1D-1Fh
20h
1Dh
1Eh
1Fh
-
-
-
-
-
-
21h
22-30h
HS TX Boost
31h
32h
33h
31h
32h
33h
-
-
-
-
-
-
Reserved
Headset Audio Mode
SMSC USB3320
Revision 1.0 (07-14-09)
DATA6S1HEET
SMSC [ SMSC CORPORATION ]
