USB 2.0 Hi-Speed Hub Controller
Datasheet
8.3.2.2
Block Read
A block read differs from a block write in that the repeated start condition exists to satisfy the I2C
specification’s requirement for a change in the transfer direction.
1
7
1
1
8
1
1
7
1
1
S
Slave Address
Wr
A
Register Address
A
S
Slave Address Rd
A
...
8
1
8
1
8
1
8
1
1
Byte Count = N
A
Data byte 1
A
Data byte 2
A
Data byte N
A
P
Block Read
Figure 8.2 Block Read
8.3.3
Invalid Protocol Response Behavior
Registers that are accessed with an invalid protocol are not updated. A register is only updated
following a valid protocol. The only valid protocols are write block and read block, which are described
above. The hub only responds to the hardware selected Slave Address (0101100x).
Attempting to communicate with the hub over SMBus with an invalid slave address or invalid protocol
results in no response, and the SMBus Slave Interface returns to the idle state.
The only valid registers that are accessible by the SMBus slave address are the registers defined in
the Registers Section. The hub does not respond to undefined registers.
8.3.4
8.3.5
General Call Address Response
The hub does not respond to a general call address of 0000_000b.
Slave Device Time-Out
According to the SMBus specification, version 1.0 devices in a transfer can abort the transfer in
progress and release the bus when any single clock low interval exceeds 25 ms (TTIMEOUT, MIN).
Devices that have detected this condition must reset their communication and be able to receive a new
START condition no later than 35 ms (TTIMEOUT, MAX).
Note: Some simple devices do not contain a clock low drive circuit; this simple kind of device typically
resets its communications port after a start or stop condition. The slave device time-out must
be implemented.
8.3.6
8.3.7
8.3.8
Stretching the SCLK Signal
The hub supports stretching of the SCLK by other devices on the SMBus. The hub does not stretch
the SCLK.
SMBus Timing
The SMBus Slave Interface complies with the SMBus AC Timing specification. See the SMBus timing
in the “Timing Diagram” section.
Bus Reset Sequence
The SMBus slave interface resets and returns to the idle state upon a START field followed
immediately by a STOP field.
Revision 1.0 (3-11-09)
54
SMSC USB251x
DATASHEET
SMSC [ SMSC CORPORATION ]
