Rise Time
Fall Time
90%
90%
Differential
Data Lines
VCRS
10%
10%
tR
tF
FIGURE 10 – DATA SIGNAL RISE AND FALL TIME
Full-Speed Buffer
Rs
TxD+
CL
Rs
TxD-
CL
Full Speed: 4 to 20ns at C = 50pF
L
The output impedance of the buffer with a series resistance
(Rs) is 28 to 44 .
Note:
Ω
Ω
FIGURE 11 – FULL SPEED LOAD
Low-Speed Buffer
Rs
Low-Speed Buffer
Rs
TxD+
TxD-
TxD+
3.6V
15K
CL
CL
CL
CL
1.5K
Rs
Rs
TxD-
15K
CL = 200pF to 600pF
CL = 50pF to 150pF
Low-Speed upstream port load
Low-Speed Downstream port load
FIGURE 12 – LOW-SPEED PORT LOADS
Round Trip
Cable Delay
80ns (max)
Driver End
of Cable
50%Point of
Initial Swing
VSS
One Way
Cable
Delay
30ns
Data Line
Crossover
Point
Receiver
End of Cable
(max)
VSS
FIGURE 13 – CABLE DELAY
SMSC DS – LPC47M14X
Page 180
Rev. 03/19/2001
SMSC [ SMSC CORPORATION ]
