6.14 GENERAL PURPOSE I/O
The LPC47M14x provides a set of flexible Input/Output control functions to the system designer through the 37
dedicated independently programmable General Purpose I/O pins (GPIO). The GPIO pins can perform basic I/O and
many of them can be individually enabled to generate an SMI and a PME.
6.14.1 GPIO Pins
The following pins include GPIO functionality. These pins are defined in the table below. All GPIOs default to the
GPIO function except for GP34 and GP35 which default to IRRX2 and IRTX2.
PIN
1
2
NAME
GP40 /DRVDEN0
GP41 /DRVDEN1 /EETI
GP42 /nIO_PME
GP43/DDRC/EETI
GP10 /J1B1
GP11 /J1B2
GP12 /J2B1
GP13 /J2B2
GP14 /J1X
GP15 /J1Y
GP16 /J2X
GP17 /J2Y
GP20 /P17
GP21 /P16 /EETI
GP22 /P12 /EETI
GP24 (SYSOPT)
GP25 /MIDI_IN
GP26 /MIDI_OUT
GP60 /LED1 /EETI
GP61 /LED2 /EETI
GP27/nIO_SMI
GP30 /FAN_TACH2
GP31 /FAN_TACH1
GP32 /FAN2
GP33 /FAN1
IRRX2/GP34
IRTX2/GP35
GP36 /nKBDRST
GP37 /A20M
GP50 /nRI2
GP51 /nDCD2
GP52 /RXD2
17
28
32
33
34
35
36
37
38
39
41
42
43
45
46
47
48
49
50
51
52
54
55
61
62
63
64
92
94
95
96
97
98
99
100
GP53 /TXD2
GP54 /nDSR2
GP55 /nRTS2
GP56 /nCTS2
GP57 /nDTR2
SMSC DS – LPC47M14X
Page 110
Rev. 03/19/2001
SMSC [ SMSC CORPORATION ]
