t1
t2
t3
nWRITE
PD<7:0>
t4
t5
t6
t7
nDATASTB
nADDRSTB
t8
t9
nWAIT
FIGURE 28 – EPP 1.9 DATA OR ADDRESS WRITE CYCLE
NAME
DESCRIPTION
MIN
60
60
0
10
5
TYP
MAX
185
185
UNITS
ns
ns
ns
ns
ns
ns
ns
t1
t2
t3
t4
t5
t6
t7
nWAIT Asserted to nWRITE Asserted (Note 1)
nWAIT Asserted to nWRITE Change (Note 1)
nWAIT Asserted to PDATA Invalid (Note 1)
PDATA Valid to Command Asserted
nWRITE to Command Asserted
nWAIT Asserted to Command Asserted (Note 1)
nWAIT Deasserted to Command Deasserted
(Note 1)
35
210
190
60
60
t8
t9
Command Asserted to nWAIT Deasserted
Command Deasserted to nWAIT Asserted
0
0
10
s
ns
Note 1: nWAIT must be filtered to compensate for ringing on the parallel bus cable. nWAIT is considered
to have settled after it does not transition for a minimum of 50 nsec.
SMSC DS – LPC47M14X
Page 187
Rev. 03/19/2001
SMSC [ SMSC CORPORATION ]
