7
RUNTIME REGISTERS
The following registers are runtime registers in the LPC47M14x. They are located at the address programmed in the
Base I/O Address in Logical Device A (also referred to as the PME register) at the offset shown. These registers are
powered by VTR.
Table 58 – Runtime Register Block Summary
REGISTER
OFFSET
HARD
SOFT
(hex)
RESET
RESET
TYPE
R/W
R
R/W
R
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R
VCC POR
VTR POR
REGISTER
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0x00
-
0x00
-
0x00
0x00
0x00
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PME_STS
Reserved – reads return 0
PME_EN
Reserved – reads return 0
PME_STS1
PME_STS2
PME_STS3
PME_STS4
PME_STS5
Reserved – reads return 0
0x00 (Note 5)
0x00 (Note 5)
-
0x00
0x00
0x00
0x00
0x00
-
PME_EN1
PME_EN2
PME_EN3
PME_EN4
PME_EN5
Reserved – reads return 0
SMI_STS 1
Note 4
Note 4
0x02 (Note 4)
(Note 4)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0x00
0x00
0x00 (Note 5)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SMI_STS 2
SMI_STS3
SMI_STS4
SMI_STS5
0x00
-
0x00
0x00
0x00
0x00
0x00
-
0x00
-
-
-
-
-
Reserved – reads return 0
SMI_EN1
SMI_EN2
SMI_EN3
SMI_EN4
SMI_EN5
Reserved – reads return 0
MSC_STS
R/W
R
R/W
R
R
-
-
Reserved – reads return 0
Force Disk Change
Floppy Data Rate Select Shadow
UART1 FIFO Control Shadow
UART2 FIFO Control Shadow
Device Disable Register
0x01
0x01
-
-
-
-
-
-
-
-
R
R/W
0x00
(Note 1)
23
24
25
26
27
28
R/W
R/W
R/W
R/W
R/W
R/W
-
-
-
-
-
-
-
-
-
-
-
-
0x01
0x01
0x01
0x01
0x01
0x01
-
-
-
-
-
-
GP10
GP11
GP12
GP13
GP14
GP15
SMSC DS – LPC47M14X
Page 125
Rev. 03/19/2001
SMSC [ SMSC CORPORATION ]
