Note that when the host is sending data to the FIFO of the FDC, the internal sector count will be complete when the FDC
reads the last byte from its side of the FIFO. There may be a delay in the removal of the transfer request signal of up to
the time taken for the FDC to read the last 16 bytes from the FIFO. The host must tolerate this delay.
Result Phase
The generation of the interrupt determines the beginning of the result phase. For each of the commands, a defined set
of result bytes has to be read from the FDC before the result phase is complete. These bytes of data must be read out
for another command to start.
RQM and DIO must both equal "1" before the result bytes may be read. After all the result bytes have been read, the
RQM and DIO bits switch to "1" and "0" respectively, and the CB bit is cleared, indicating that the FDC is ready to accept
the next command.
SMSC LPC47B27x
- 36 -
Rev. 08-10-04
DATASHEET
SMSC [ SMSC CORPORATION ]
