USB 2.0 Hub and 10/100 Ethernet Controller
Datasheet
1.1.2
USB Hub
The integrated USB hub is fully compliant with the USB 2.0 Specification and will attach to a USB host
as a Full-Speed Hub or as a Full-/High-Speed Hub. The hub supports Low-Speed, Full-Speed, and
High-Speed (if operating as a High-Speed hub) downstream devices on all of the enabled downstream
ports.
A dedicated Transaction Translator (TT) is available for each downstream facing port. This architecture
ensures maximum USB throughput for each connected device when operating with mixed-speed
peripherals.
The hub works with an external USB power distributed switch device to control VBUS switching to
downstream ports, and to limit current and sense over-current conditions.
All required resistors on the USB ports are integrated into the hub. This includes all series termination
resistors on D+ and D- pins and all required pull-down and pull-up resistors on D+ and D- pins. The
over-current sense inputs for the downstream facing ports have internal pull-up resistors.
Four external ports are available for general USB device connectivity.
1.1.3
Ethernet Controller
The 10/100 Ethernet controller provides an integrated Ethernet MAC and PHY which are fully IEEE
802.3 10BASE-T and 802.3u 100BASE-TX compliant. The 10/100 Ethernet controller also supports
numerous power management wakeup features, including “Magic Packet”, “Wake on LAN” and “Link
Status Change”. These wakeup events can be programmed to initiate a USB remote wakeup.
The 10/100 Ethernet PHY integrates an IEEE 802.3 physical layer for twisted pair Ethernet
applications. The PHY block includes support for auto-negotiation, full or half-duplex configuration,
auto-polarity correction and Auto-MDIX. Minimal external components are required for the utilization of
the integrated PHY.
The Ethernet controller implements four USB endpoints: Control, Interrupt, Bulk-in, and Bulk-out. The
Bulk-in and Bulk-out Endpoints allow for Ethernet reception and transmission respectively.
Implementation of vendor-specific commands allows for efficient statistics gathering and access to the
Ethernet controller’s system control and status registers.
1.1.4
1.1.5
EEPROM Controller
The LAN9514/LAN9514i contains an EEPROM controller for connection to an external EEPROM. This
allows for the automatic loading of static configuration data upon power-on reset, pin reset, or software
reset. The EEPROM can be configured to load USB descriptors, USB device configuration, and the
MAC address.
Peripherals
The LAN9514/LAN9514i also contains a TAP controller, and provides three PHY LED indicators, as
well as eight general purpose I/O pins. All GPIOs can serve as remote wakeup events when
LAN9514/LAN9514i is in a suspended state.
The integrated IEEE 1149.1 compliant TAP controller provides boundary scan via JTAG.
1.1.6
Power Management
The LAN9514/LAN9514i features three variations of USB suspend: SUSPEND0, SUSPEND1, and
SUSPEND2. These modes allow the application to select the ideal balance of remote wakeup
functionality and power consumption.
SUSPEND0: Supports GPIO, “Wake On LAN”, and “Magic Packet” remote wakeup events. This
suspend state reduces power by stopping the clocks of the MAC and other internal modules.
SMSC LAN9514/LAN9514i
7
Revision 1.0 (11-24-09)
DATASHEET
SMSC [ SMSC CORPORATION ]
