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LAN9313I 参数 Datasheet PDF下载

LAN9313I图片预览
型号: LAN9313I
PDF下载: 下载PDF文件 查看货源
内容描述: 三端口10/100管理型以太网交换机MII [Three Port 10/100 Managed Ethernet Switch with MII]
分类和应用: 以太网局域网(LAN)标准
文件页数/大小: 398 页 / 4083 K
品牌: SMSC [ SMSC CORPORATION ]
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Three Port 10/100 Managed Ethernet Switch with MII  
Datasheet  
Chapter 7 Ethernet PHYs  
7.1  
Functional Overview  
The LAN9313/LAN9313i contains three PHYs: Port 1 PHY, Port 2 PHY and a Virtual PHY. The Port 1  
& 2 PHYs are identical in functionality and each connect their corresponding Ethernet signal pins to  
the switch fabric MAC of their respective port. These PHYs interface with their respective MAC via an  
internal MII interface. The Virtual PHY provides the virtual functionality of a PHY and allows connection  
of an external MAC to port 0 of the switch fabric as if it was connected to a single port PHY. All PHYs  
comply with the IEEE 802.3 Physical Layer for Twisted Pair Ethernet and can be configured for full/half  
duplex 100 Mbps (100BASE-TX) or 10Mbps (10BASE-T) Ethernet operation. All PHY registers follow  
the IEEE 802.3 (clause 22.2.4) specified MII management register set and can be configured indirectly  
via the external MII interface signals, or directly via the memory mapped Virtual PHY registers. In  
addition, the Port 1 PHY and Port 2 PHY can be configured via the PHY Management Interface (PMI).  
Refer to Section 13.2, "Ethernet PHY Control and Status Registers" for details on the Ethernet PHY  
registers.  
The LAN9313/LAN9313i Ethernet PHYs are discussed in detail in the following sections:  
„
„
Section 7.2, "Port 1 & 2 PHYs," on page 85  
Section 7.3, "Virtual PHY," on page 98  
7.1.1  
PHY Addressing  
Each individual PHY is assigned a unique default PHY address via the phy_addr_sel_strap  
configuration strap as shown in Table 7.1. In addition, the Port 1 PHY and Port 2 PHY addresses can  
be changed via the PHY Address (PHYADD) field in the Port x PHY Special Modes Register  
(PHY_SPECIAL_MODES_x). For proper operation, all LAN9313/LAN9313i PHY addresses must be  
unique. No check is performed to assure each PHY is set to a different address. Configuration strap  
values are latched upon the de-assertion of a chip-level reset as described in Section 4.2.4,  
"Configuration Straps," on page 45.  
Table 7.1 Default PHY Serial MII Addressing  
VIRTUAL PHY DEFAULT  
ADDRESS VALUE  
PORT 1 PHY DEFAULT PORT 2 PHY DEFAULT  
PHY_ADDR_SEL_STRAP  
ADDRESS VALUE  
ADDRESS VALUE  
0
1
0
1
1
2
2
3
Revision 1.2 (04-08-08)  
SMSC LAN9313/LAN9313i  
DATA8S4HEET  
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