High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
BITS
DESCRIPTION
TYPE
DEFAULT
12
11
Reserved
RO
-
TX Data FIFO Underrun Interrupt (TDFU). Generated when the TX data
FIFO underruns.
R/WC
0
10
9
TX Data FIFO Overrun Interrupt (TDFO). Generated when the TX data
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
0
0
FIFO is full, and another write is attempted.
TX Data FIFO Available Interrupt (TDFA). Generated when the TX data
FIFO available space is greater than the programmed level.
8
TX Status FIFO Full Interrupt (TSFF). Generated when the TX Status
FIFO is full.
0
7
TX Status FIFO Level Interrupt (TSFL). Generated when the TX Status
FIFO reaches the programmed level.
0
6
RX Dropped Frame Interrupt (RXDF_INT). This interrupt is issued
whenever a receive frame is dropped.
0
5
RX Data FIFO Level Interrupt (RDFL). Generated when the RX FIFO
reaches the programmed level.
0
4
RX Status FIFO Full Interrupt (RSFF). Generated when the RX Status
FIFO is full.
0
3
RX Status FIFO Level Interrupt (RSFL). Generated when the RX Status
FIFO reaches the programmed level.
0
2-0
GPIO [2:0] (GPIOx_INT). Interrupts are generated from the GPIO’s.
These interrupts are configured through the GPIO_CFG register.
000
SMSC LAN9218
Revision 1.5 (07-18-06)
DATA7S1HEET
SMSC [ SMSC CORPORATION ]
