High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
1.2
Internal Block Overview
This section provides an overview of each of these functional blocks as shown in Figure 1.2, "Internal
Block Diagram".
25MHz
EEPROM
(Optional)
+3.3V
EEPROM
Controller
3.3V to 1.8V
Regulator
PME
Wakup Indicator
PLL
Power Management
2kB to 14kB
Configurable TX FIFO
Host Bus Interface
(HBI)
SRAM I/F
TX Status FIFO
RX Status FIFO
10/100
Ethernet
10/100
Ethernet
PHY
PIO Controller
LAN
MAC
IRQ
Interrupt
Controller
MIL - RX Elastic
Buffer - 128 bytes
FIFO_SEL
2kB to 14kB
Configurable RX FIFO
MIL - TX Elastic
Buffer - 2K bytes
GP Timer
Figure 1.2 Internal Block Diagram
1.3
1.4
10/100 Ethernet PHY
The LAN9218 integrates an IEEE 802.3 physical layer for twisted pair Ethernet applications. The PHY
can be configured for either 100 Mbps (100Base-TX) or 10 Mbps (10Base-T) Ethernet operation in
either full or half duplex configurations. The PHY block supports HP Auto-MDIX and auto-negotiation.
Minimal external components are required for the utilization of the Integrated PHY.
10/100 Ethernet MAC
The transmit and receive data paths are separate within the MAC allowing the highest performance
especially in full duplex mode. The data paths connect to the PIO interface Function via separate
busses to increase performance. Payload data as well as transmit and receive status is passed on
these busses.
A third internal bus is used to access the MAC’s Control and Status Registers (CSR’s). This bus is
accessible from the host through the PIO interface function.
On the backend, the MAC interfaces with the internal 10/100 PHY through a the MII (Media
Independent Interface) port internal to the LAN9218. The MAC CSR's also provides a mechanism for
accessing the PHY’s internal registers through the internal SMI (Serial Management Interface) bus.
SMSC LAN9218
11
Revision 1.5 (07-18-06)
DATASHEET
SMSC [ SMSC CORPORATION ]
