High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
Datasheet
3.8.2.1
Supported EEPROM Operations
The EEPROM controller supports the following EEPROM operations under host control via the
E2P_CMD register. The operations are commonly supported by “93C46” EEPROM devices. A
description and functional timing diagram is provided below for each operation. Please refer to the
E2P_CMD register description in Section 5.3.23, "E2P_CMD – EEPROM Command Register," on
page 92 for E2P_CMD field settings for each command.
ERASE (Erase Location): If erase/write operations are enabled in the EEPROM, this command will
erase the location selected by the EPC Address field (EPC_ADDR). The EPC_TO bit is set if the
EEPROM does not respond within 30ms.
tCSL
EECS
EECLK
1
1
1
A6
A0
EEDIO (OUTPUT)
EEDIO (INPUT)
Figure 3.3 EEPROM ERASE Cycle
ERAL (Erase All): If erase/write operations are enabled in the EEPROM, this command will initiate a
bulk erase of the entire EEPROM.The EPC_TO bit is set if the EEPROM does not respond within
30ms.
tCSL
EECS
EECLK
1
0
0
1
0
EEDIO (OUTPUT)
EEDIO (INPUT)
Figure 3.4 EEPROM ERAL Cycle
Revision 1.8 (06-06-07)
32
SMSC LAN9218i
DATASHEET
SMSC [ SMSC CORPORATION ]
