High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX & Industrial Temperature Support
Datasheet
5.4.6
MII_ACC—MII Access Register
Offset:
6
Attribute:
Size:
R/W
Default Value:
00000000h
32 bits
This register is used to control the Management cycles to the PHY.
BITS
DESCRIPTION
31-16
15-11
10-6
5-2
Reserved
PHY Address: For every access to this register, this field must be set to 00001b.
MII Register Index (MIIRINDA): These bits select the desired MII register in the PHY.
Reserved
1
MII Write (MIIWnR): Setting this bit tells the PHY that this will be a write operation using the MII data
register. If this bit is not set, this will be a read operation, packing the data in the MII data register.
0
MII Busy (MIIBZY): This bit must be polled to determine when the MII register access is complete.
This bit must read a logical 0 before writing to this register and MII data register.
The LAN driver software must set (1) this bit in order for the LAN9218I to read or write any of the MII
PHY registers.
During a MII register access, this bit will be set, signifying a read or write access is in progress. The
MII data register must be kept valid until the MAC clears this bit during a PHY write operation. The
MII data register is invalid until the MAC has cleared this bit during a PHY read operation.
5.4.7
MII_DATA—MII Data Register
Offset:
7
Attribute:
Size:
R/W
Default Value:
00000000h
32 bits
This register contains either the data to be written to the PHY register specified in the MII Access
Register, or the read data from the PHY register whose index is specified in the MII Access Register.
BITS
31-16
15-0
DESCRIPTION
Reserved
MII Data. This contains the 16-bit value read from the PHY read operation or the 16-bit data value to
be written to the PHY before an MII write operation.
SMSC LAN9218I
Revision 1.5 (07-18-06)
DATA9S9HEET
SMSC [ SMSC CORPORATION ]
