High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX & Industrial Temperature Support
Datasheet
5.5.1
Basic Control Register
Index (In Decimal):
0
Size:
16-bits
BITS
DESCRIPTION
TYPE
DEFAULT
15
Reset. 1 = software reset. Bit is self-clearing. For best results, when setting
this bit do not set other bits in this register.
RW/SC
0
14
13
Loopback. 1 = loopback mode, 0 = normal operation
RW
RW
0
Speed Select. 1 = 100Mbps, 0 = 10Mbps. Ignored if Auto Negotiation is
enabled (0.12 = 1).
See Note 5.1
12
11
Auto-Negotiation Enable. 1 = enable auto-negotiate process (overrides
RW
RW
See Note 5.1
0
0.13 and 0.8) 0 = disable auto-negotiate process.
Power Down. 1 = General power down-mode, 0 = normal operation.
Note:
After this bit is cleared, the PHY may auto-negotiate with it's
partner station. This process may take a few seconds to complete.
Once auto-negotiation is complete, bit 5 of the PHY's Basic Status
Register will be set.
10
9
Reserved
RO
0
0
Restart Auto-Negotiate. 1 = restart auto-negotiate process 0 = normal
operation. Bit is self-clearing.
RW/SC
8
Duplex Mode. 1 = full duplex, 0 = half duplex. Ignored if Auto Negotiation
is enabled (0.12 = 1).
RW
0
7
Collision Test. 1 = enable COL test, 0 = disable COL test
RW
RO
0
0
6-0
Reserved
Note 5.1 This default value of this bit is determined by Pin 74 "SPEED_SEL". Please refer to the
pin description section for more details
Revision 1.5 (07-18-06)
104
SMSC LAN9218I
DATASHEET
SMSC [ SMSC CORPORATION ]
