16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
BITS
DESCRIPTION
TYPE
DEFAULT
11-9
8
Reserved
RO
-
IRQ Enable (IRQ_EN) – This bit controls the final interrupt output to the
IRQ pin. When clear, the IRQ output is disabled and permanently
deasserted. This bit has no effect on any internal interrupt status bits.
R/W
0
7-5
4
Reserved
RO
-
IRQ Polarity (IRQ_POL) – When cleared, enables the IRQ line to
function as an active low output. When set, the IRQ output is active high.
When IRQ is configured as an open-drain output this field is ignored,
and the interrupt output is always active low.
R/W
NASR
0
3-1
0
Reserved
RO
-
IRQ Buffer Type (IRQ_TYPE) – When cleared, enables IRQ to function
as an open-drain buffer for use in a Wired-Or Interrupt configuration.
When set, the IRQ output is a Push-Pull driver. When configured as an
open-drain output the IRQ_POL field is ignored, and the interrupt output
is always active low.
R/W
NASR
0
Revision 1.8 (06-06-07)
74
SMSC LAN9217
DATASHEET
SMSC [ SMSC CORPORATION ]
