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LAN9217_07 参数 Datasheet PDF下载

LAN9217_07图片预览
型号: LAN9217_07
PDF下载: 下载PDF文件 查看货源
内容描述: 16位高性能单芯片10/100以太网控制器与HP Auto-MDIX的 [16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX]
分类和应用: 控制器以太网局域网(LAN)标准
文件页数/大小: 137 页 / 1566 K
品牌: SMSC [ SMSC CORPORATION ]
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16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX  
Datasheet  
3.13.2  
RX Packet Format  
The RX status words can be read from the RX status FIFO port, while the RX data packets can be  
read from the RX data FIFO. RX data packets are formatted in a specific manner before the host can  
read them as shown in Figure 3.18. It is assumed that the host has previously read the associated  
status word from the RX status FIFO, to ascertain the data size and any error conditions.  
Host Read  
Order  
31  
0
Optional offset DWORD0  
1st  
2nd  
.
.
Optional offset DWORDn  
ofs + First Data DWORD  
.
.
.
.
Last Data DWORD  
Optional Pad DWORD0  
.
.
Optional Pad DWORDn  
Last  
Figure 3.18 RX Packet Format  
Note 3.16 The LAN9217 host bus interface supports 16-bit bus transfers; internally, all data paths are  
32-bits wide. Figure 3.18 describes the host read ordering for pairs of atomic 16-bit  
transactions.  
3.13.3  
RX Status Format  
BITS  
31  
DESCRIPTION  
Reserved. This bit is reserved. Reads 0.  
30  
Filtering Fail. When set, this bit indicates that the associated frame failed the address recognizing  
filtering.  
29:16  
15  
Packet Length. The size, in bytes, of the corresponding received frame.  
Error Status (ES). When set this bit indicates that the MIL has reported an error. This bit is the  
Internal logical “or” of bits 11,7,6 and 1.  
14  
13  
Reserved. These bits are reserved. Reads 0.  
Broadcast Frame. When set, this bit indicates that the received frame has a Broadcast address.  
Revision 1.8 (06-06-07)  
58  
SMSC LAN9217  
DATASHEET