16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
init
Idle
TX Status
Available
Read TX
Status
(optional)
Check
available
FIFO
space
Write
TX
Command
Write
Start
Padding
(optional)
Last Buffer in
Packet
Not Last Buffer
Write
Buffer
Figure 3.12 Simplified Host TX Flow Diagram
3.12.1
TX Buffer Format
TX buffers exist in the host’s memory in a given format. The host writes a TX command word into the
TX data buffer before moving the Ethernet packet data. The TX command A and command B are 32-
bit values that are used by the LAN9217 in the handling and processing of the associated Ethernet
packet data buffer. Buffer alignment, segmentation and other packet processing parameters are
included in the command structure. The following diagram illustrates the buffer format.
SMSC LAN9217
45
Revision 1.8 (06-06-07)
DATASHEET
SMSC [ SMSC CORPORATION ]
