欢迎访问ic37.com |
会员登录 免费注册
发布采购

LAN9217-MT-E2 参数 Datasheet PDF下载

LAN9217-MT-E2图片预览
型号: LAN9217-MT-E2
PDF下载: 下载PDF文件 查看货源
内容描述: 16位高性能单芯片10/100以太网控制器与HP Auto-MDIX的 [16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX]
分类和应用: 控制器以太网局域网(LAN)标准
文件页数/大小: 134 页 / 1591 K
品牌: SMSC [ SMSC CORPORATION ]
 浏览型号LAN9217-MT-E2的Datasheet PDF文件第118页浏览型号LAN9217-MT-E2的Datasheet PDF文件第119页浏览型号LAN9217-MT-E2的Datasheet PDF文件第120页浏览型号LAN9217-MT-E2的Datasheet PDF文件第121页浏览型号LAN9217-MT-E2的Datasheet PDF文件第123页浏览型号LAN9217-MT-E2的Datasheet PDF文件第124页浏览型号LAN9217-MT-E2的Datasheet PDF文件第125页浏览型号LAN9217-MT-E2的Datasheet PDF文件第126页  
16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX  
Datasheet  
6.3  
PIO Burst Reads  
In this mode, performance is improved by allowing up to 16 WORD read cycles back-to-back. PIO  
Burst Reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both of these  
control signals must go high between bursts for the period specified.  
A[7:5]  
A[4:1]  
nCS, nRD  
Data Bus  
Figure 6.2 PIO Burst Read Cycle Timing  
Note: The “Data Bus” width is 16 bits  
Table 6.4 PIO Burst Read Timing  
SYMBOL  
DESCRIPTION  
MIN  
TYP  
MAX  
UNITS  
tcsh  
tcsdv  
tacyc  
tasu  
tadv  
tah  
nCS, nRD Deassertion Time  
nCS, nRD Valid to Data Valid  
Address Cycle Time  
13  
ns  
ns  
30  
45  
0
Address Setup to nCS, nRD valid  
Address Stable to Data Valid  
Address Hold Time  
ns  
40  
7
0
0
ns  
ns  
ns  
ns  
tdon  
tdoff  
tdoh  
Data Buffer Turn On Time  
Data Buffer Turn Off Time  
Data Output Hold Time  
0
Note: A PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when  
either or both nCS and nRD are deasserted. They may be asserted and deasserted in any  
order.  
Revision 1.5 (07-18-06)  
122  
SMSC LAN9217  
DATASHEET