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LAN9217-MT-E2 参数 Datasheet PDF下载

LAN9217-MT-E2图片预览
型号: LAN9217-MT-E2
PDF下载: 下载PDF文件 查看货源
内容描述: 16位高性能单芯片10/100以太网控制器与HP Auto-MDIX的 [16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX]
分类和应用: 控制器以太网局域网(LAN)标准
文件页数/大小: 134 页 / 1591 K
品牌: SMSC [ SMSC CORPORATION ]
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16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX  
Datasheet  
5.5.10  
Special Control/Status Indications  
Index (In Decimal):  
27  
Size:  
16-bits  
ADDRESS  
DESCRIPTION  
MODE  
DEFAULT  
15  
Override AMDIX Strap  
RW  
0
0 - AMDIX_EN (pin 73) enables or disables HP Auto MDIX  
1 - Override pin 73. PHY Register 27.14 and 27.13 determine MDIX  
function  
14  
13  
Auto-MDIX Enable: Only effective when 27.15=1, otherwise ignored.  
0 = Disable Auto-MDIX. 27.13 determines normal or reversed connection.  
1 = Enable Auto-MDIX. 27.13 must be set to 0.  
RW  
RW  
0
0
Auto-MDIX State. Only effective when 27.15=1, otherwise ignored.  
When 27.14 = 0 (manually set MDIX state):  
0 = no crossover (TPO = output, TPI = input)  
1 = crossover (TPO = input, TPI = output)  
When 27.14 = 1 (automatic MDIX) this bit must be set to 0.  
Do not use the combination 27.15=1, 27.14=1, 27.13=1.  
12:11  
10  
Reserved: Write as 0. Ignore on read.  
RW  
0
0
VCOOFF_LP: Forces the Receive PLL 10M to lock on the reference clock  
at all times:  
RW,  
NASR  
0 - Receive PLL 10M can lock on reference or line as needed (normal  
operation)  
1 - Receive PLL 10M is locked on the reference clock.  
In this mode 10M data packets cannot be received.  
9-5  
4
Reserved: Write as 0. Ignore on read.  
RW  
RO  
0
0
XPOL: Polarity state of the 10Base-T:  
0 - Normal polarity  
1 - Reversed polarity  
3:0  
Reserved: Read only - Writing to these bits have no effect.  
RO  
1011b  
SMSC LAN9217  
115  
Revision 1.5 (07-18-06)  
DATASHEET