Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
and will determine the required wait-time. In this case the TX_CLK and RX_CLK period for
the internal PHY is 400ns, therefore the host must wait 2us (5*400ns) before proceeding. If
the clocks of the device being deselected by the switch are not running, they are not
considered in this calculation.
Set EXT_PHY_SEL described in Section 5.3.9, "HW_CFG—Hardware Configuration Register" to
the desired MII port. This step switches the RXD[3:0], RX_DV, RX_ER, TXD[3:0], TX_EN, CRS
and COL signals to the desired port.
Set PHY_CLK_SEL described in Section 5.3.9, "HW_CFG—Hardware Configuration Register" to
the desired port. This must be the same port that is selected by EXT_PHY_SEL.
The host must wait a period of time of not less than 5 cycles of the slowest, newly enabled clock
before executing the next step in this procedure.
Enable the LAN9215 transmitter.
Enable the LAN9215 receiver.
The process is complete. The LAN9215 is now operational using the newly selected MII device.
The above procedure must be repeated each time the MII port is switched. The procedure is identical
when switching from internal PHY to external MII, or vice-versa.
Revision 1.5 (07-18-06)
SMSC LAN9215
DATA4S2HEET
SMSC [ SMSC CORPORATION ]
