Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
Table 2.5 System and Power Signals (continued)
PIN
NO.
BUFFER
TYPE
NUM
PINS
NAME
SYMBOL
DESCRIPTION
3,65
Core Voltage
Decoupling
VDD_CORE
P
2
1.8 V from internal core regulator.
Both pins must be connected
together externally and then tied to a
10uF 0.1-Ohm ESR capacitor, in
parallel with a 0.01uF capacitor to
Ground next to each pin. See
Note 2.1
1,66
7
Core Ground
PLL Power
GND_CORE
VDD_PLL
P
P
2
1
Ground for internal digital logic
1.8V Power from the internal PLL
regulator. This external pin must be
connected to a 10uF 0.1-Ohm ESR
capacitor, in parallel with a 0.01uF
capacitor to Ground. See Note 2.1
4
8
PLL Ground
VSS_PLL
VDD_REF
P
P
1
1
GND for the PLL
Reference Power
Connected to 3.3v power and used
as the reference voltage for the
internal PLL
11
Reference Ground
VSS_REF
P
1
Ground for internal PLL reference
voltage
Note 2.1 Please refer to the SMSC application note AN 12.5x, entitled "Designing with the LAN9218
Family - Getting Started". It is also important to note that this application note applies to
the whole SMSC LAN9118 family of Ethernet controllers. However, subtle differences may
apply.
SMSC LAN9215
Revision 1.5 (07-18-06)
DATA1S9HEET
SMSC [ SMSC CORPORATION ]
