Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
Datasheet
BITS
DESCRIPTION
TYPE
DEFAULT
0
Flow Control on Any Frame (FCANY). When this bit is set, the LAN9215i
will assert back pressure, or transmit a pause frame when the AFC level is
reached and any frame is received. Setting this bit enables full-duplex flow
control when the LAN9215i is operating in full-duplex mode.
R/W
0
When this mode is enabled during half-duplex operation, the Flow Controller
does not decode the MAC address and will send a pause frame upon
receipt of a valid preamble (i.e., immediately at the beginning of the next
frame after the RX data FIFO level is reached).
When this mode is enabled during full-duplex operation, the Flow Controller
will immediately instruct the MAC to send a pause frame when the RX data
FIFO level is reached. The MAC will queue the pause frame transmission
for the next available window.
Setting this bit overrides bits [3:1] of this register.
Table 5.5 Backpressure Duration Bit Mapping
BACKPRESSURE DURATION
[19:16]
0h
100Mbs Mode
5uS
10Mbs Mode
7.2uS
1h
10uS
12.2uS
2h
15uS
17.2uS
3h
25uS
27.2uS
4h
50uS
52.2uS
5h
100uS
150uS
200uS
250uS
300uS
350uS
400uS
450uS
500uS
550uS
600uS
102.2uS
152.2uS
202.2uS
252.2uS
302.2uS
352.2uS
402.2uS
452.2uS
502.2uS
552.2uS
602.2uS
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
Revision 1.93 (12-12-07)
96
SMSC LAN9215i
DATASHEET
SMSC [ SMSC CORPORATION ]
