Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
Datasheet
5.3.8
TX_CFG—Transmit Configuration Register
Offset:
70h
Size:
32 bits
This register controls the transmit functions on the LAN9215i Ethernet Controller.
BITS
31-16
15
DESCRIPTION
TYPE
RO
DEFAULT
Reserved.
-
Force TX Status Discard (TXS_DUMP). This self-clearing bit clears the TX
status FIFO of all pending status DWORD’s. When a ‘1’ is written, the TX
status pointers are cleared to zero.
SC
0
14
Force TX Data Discard (TXD_DUMP). This self-clearing bit clears the TX
data FIFO of all pending data. When a ‘1’ is written, the TX data pointers
are cleared to zero.
SC
0
13-3
2
Reserved
RO
-
TX Status Allow Overrun (TXSAO). When this bit is cleared, data
transmission is suspended if the TX Status FIFO becomes full. Setting this
bit high allows the transmitter to continue operation with a full TX Status
FIFO.
R/W
0
Note:
This bit does not affect the operation of the TX Status FIFO Full
interrupt.
1
0
Transmitter Enable (TX_ON). When this bit is set (1), the transmitter is
enabled. Any data in the TX FIFO will be sent. This bit is cleared
automatically when STOP_TX is set and the transmitter is halted.
R/W
SC
0
0
Stop Transmitter (STOP_TX). When this bit is set (1), the transmitter will
finish the current frame, and will then stop transmitting. When the transmitter
has stopped this bit will clear. All writes to this bit are ignored while this bit
is high.
SMSC LAN9215i
81
Revision 1.93 (12-12-07)
DATASHEET
SMSC [ SMSC CORPORATION ]
