Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
Datasheet
3.10.5.2
PHY Soft Reset via PHY Basic Control Register (PHY Reg. 0.15)
The PHY Reg. 0.15 Soft Reset is initiated by writing a ‘1’ to bit 15 of the PHY’s Basic Control Register.
This self-clearing bit will return to ‘0’ at which time the PHY reset is complete.
3.11
MII Interface - External MII Switching
There are two mechanisms that are used to switch between the internal PHY and the external MII port.
A LAN driver or other software controlled mechanism is used to control the PHY_CLK_SEL[1:0]
bits described in Section 5.3.9, "HW_CFG—Hardware Configuration Register" that provides glitch-
free MII clock switching. This mechanism allows the host processor to disable (gate) the RX_CLK
and TX_CLK clocks from both the internal PHY and the external MII port, and switch the clock
sources once they have stopped. After switching the clocks, the LAN9215i transmitter and receiver
can be re-enabled.
A simple multiplexor that, with the exception of the SMI bus and the MII clocks, will switch the
remaining MII signals. This multiplexor is controlled by the EXT_PHY_EN bit described in Section
5.3.9, "HW_CFG—Hardware Configuration Register"
3.11.1
SMI Switching
The Serial Management Interface (SMI) port can be switched between the internal PHY and external
MII ports based on the settings of the SMI_SEL bit described in Section 5.3.9, "HW_CFG—Hardware
Configuration Register". The SMI port can be switched independent of the setting of the other MII
signals.
APPLICATION NOTE: The user is cautioned to not switch the SMI port while an SMI transaction is in progress.
3.11.2
MII Clock Switching
The LAN9215i supports dynamic switching between the integrated internal PHY and the external MII
port which can connect to an external MII compatible Ethernet PHY device.
The remaining MII signals, with the exception of the SMI port, are switched using a simple multiplexor
controlled by the EXT_PHY_SEL bit described in Section 5.3.9, "HW_CFG—Hardware Configuration
Register". It is required that the MII clocks be disabled before the other MII signals are switched.
The steps outlined in the flow diagram in Figure 3.11, "MII Switching Procedure", detail the required
procedure for switching the MII port, including the MII clocks. These steps must be followed in order
to guarantee clean switching of the MII ports.
Using the SMI interface, both the internal PHY, and the external PHY must be placed in a stable state.
For each device generating a TX_CLK or RX_CLK, this clock must be stable and glitch-free before the
switch can be made. If either device is not generating a TX_CLK or RX_CLK, this clock must remain
off until the switch is complete. In either case the TX_CLK and RX_CLK must be stable and glitch-free
for the device that will be selected after the switch. The following must be done prior to a switch:
The LAN9215i Transmitter must be halted.
The halting of the LAN9215i transmitter must be complete
The LAN9215i Receiver must be halted.
The halting of the LAN9215i receiver must be complete.
The PHY_CLK_SEL field must be set to 10b. This action will disable the MII clocks to the LAN9215i
internal logic for both the internal PHY, and the external MII interface.
The host must wait a period of time not less than 5 cycles of the slowest operating clock before
executing the next step in this procedure.
APPLICATION NOTE: For example, if the internal PHY was operating in 10Mbs mode, and the external PHY was
operating at 100Mbs mode, the internal PHY’s TX_CLK and RX_CLK period is the longest,
SMSC LAN9215i
43
Revision 1.93 (12-12-07)
DATASHEET
SMSC [ SMSC CORPORATION ]
