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LAN9215I_07 参数 Datasheet PDF下载

LAN9215I_07图片预览
型号: LAN9215I_07
PDF下载: 下载PDF文件 查看货源
内容描述: 高效的单芯片10/100以太网控制器与HP Auto-MDIX的和工业温度支持 [Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support]
分类和应用: 控制器以太网局域网(LAN)标准
文件页数/大小: 138 页 / 1665 K
品牌: SMSC [ SMSC CORPORATION ]
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Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support  
Datasheet  
6.1.2  
Special Restrictions on Back-to-Back Read Cycles  
There are also restrictions on specific back-to-back read operations. These restrictions concern  
reading specific registers after reading resources that have side effects. In many cases there is a delay  
between reading the LAN9215i, and the subsequent indication of the expected change in the control  
register values.  
In order to prevent the host from reading stale data on back-to-back reads, minimum wait periods have  
been established. These periods are specified in Table 6.2, "Read After Read Timing Rules". The host  
processor is required to wait the specified period of time between read operations of specific  
combinations of resources. The wait period is dependant upon the combination of registers being read.  
Performing "dummy" reads of the BYTE_TEST register is a convenient way to guarantee that the  
minimum wait time restriction is met. Table 6.2 also shows the number of dummy reads that are  
required for back-to-back read operations. The number of BYTE_TEST reads in this table is based on  
the minimum timing for Tcycle (165ns). For microprocessors with slower busses the number of reads  
may be reduced as long as the total time is equal to, or greater than the time specified in the table.  
Dummy reads of the BYTE_TEST register are not required as long as the minimum time period is met.  
Table 6.2 Read After Read Timing Rules  
OR PERFORM THIS MANY  
READS OF BYTE_TEST…  
(ASSUMING Tcycle OF  
AFTER  
READING...  
WAIT FOR THIS MANY  
NS…  
165NS)  
BEFORE READING...  
RX Data FIFO  
RX Status FIFO  
TX Status FIFO  
RX_DROP  
165  
165  
165  
330  
330  
1
1
1
2
2
RX_FIFO_INF  
RX_FIFO_INF  
TX_FIFO_INF  
RX_DROP  
RX_DP_CTRL  
TX Status FIFO  
RX Status FIFO  
Note 6.1  
Note 6.1 This restriction is only applicable after a fast-forward operation has been completed and  
the RX_FFWD bit has been cleared. Refer to Section 3.13.1.1, "Receive Data FIFO Fast  
Forward," on page 57 for more information.  
Revision 1.93 (12-12-07)  
122  
SMSC LAN9215i  
DATASHEET