Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
Datasheet
Host Read
Order
31
0
Optional offset DWORD0
1st
2nd
.
.
Optional offset DWORDn
ofs + First Data DWORD
.
.
.
.
Last Data DWORD
Optional Pad DWORD0
.
.
Optional Pad DWORDn
Last
Figure 3.18 RX Packet Format
Note 3.16 The LAN9215I host bus interface supports 16-bit bus transfers; internally, all data paths
are 32-bits wide. Figure 3.18 describes the host read ordering for pairs of atomic 16-bit
transactions.
3.15.3
RX Status Format
BITS
31
DESCRIPTION
Reserved. This bit is reserved. Reads 0.
30
Filtering Fail. When set, this bit indicates that the associated frame failed the address recognizing
filtering.
29:16
15
Packet Length. The size, in bytes, of the corresponding received frame.
Error Status (ES). When set this bit indicates that the MIL has reported an error. This bit is the
Internal logical “or” of bits 11,7,6 and 1.
14
13
12
Reserved. These bits are reserved. Reads 0.
Broadcast Frame. When set, this bit indicates that the received frame has a Broadcast address.
Length Error (LE). When set, this bit indicates that the actual length does not match with the
length/type field of the received frame.
Revision 1.5 (07-18-06)
SMSC LAN9215I
DATA5S8HEET
SMSC [ SMSC CORPORATION ]
