Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
Datasheet
Host Write
Order
31
0
TX Command 'A'
TX Command 'B'
1st
2nd
3rd
Optional offset DWORD0
.
.
.
Optional offset DWORDn
Offset + Data DWORD0
.
.
.
.
.
Last Data & PAD
Optional Pad DWORD0
.
.
.
Last
Optional Pad DWORDn
Figure 3.13 TX Buffer Format
Figure 3.13, "TX Buffer Format", shows the TX Buffer as it is written into the LAN9215I. It should be
noted that not all of the data shown in this diagram is actually stored in the TX data FIFO. This must
be taken into account when calculating the actual TX data FIFO usage. Please refer to Section 3.14.5,
"Calculating Actual TX Data FIFO Usage," on page 50 for a detailed explanation on calculating the
actual TX data FIFO usage.
Note 3.14 The LAN9215I host bus interface supports 16-bit bus transfers; internally, all data paths
are 32-bits wide. Figure 3.13 describes the host write ordering for pairs of atomic 16-bit
transactions.
3.14.2
TX Command Format
The TX command instructs the TX FIFO controller on handling the subsequent buffer. The command
precedes the data to be transmitted. The TX command is divided into two, 32-bit words; TX command
‘A’ and TX command ‘B’.
There is a 16-bit packet tag in the TX command ‘B’ command word. Packet tags may, if host software
desires, be unique for each packet (i.e., an incrementing count). The value of the tag will be returned
in the RX status word for the associated packet. The Packet tag can be used by host software to
uniquely identify each status word as it is returned to the host.
Both TX command ‘A’ and TX command ‘B’ are required for each buffer in a given packet. TX
command ‘B’ must be identical for every buffer in a given packet. If the TX command ‘B’ words do not
match, the Ethernet controller will assert the Transmitter Error (TXE) flag.
Revision 1.5 (07-18-06)
SMSC LAN9215I
DATA4S6HEET
SMSC [ SMSC CORPORATION ]
