Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
Datasheet
If an operation is attempted, and an EEPROM device does not respond within 30mS, the LAN9215I
will timeout, and the EPC timeout bit (EPC_TO) in the E2P_CMD register will be set.
Figure 3.2, "EEPROM Access Flow Diagram" illustrates the host accesses required to perform an
EEPROM Read or Write operation.
EEPROM Write
EEPROM Read
Idle
Idle
Write
Command
Register
Write Data
Register
Write
Read
Command
Command
Register
Register
Busy Bit = 0
Read
Command
Register
Read Data
Register
Busy Bit = 0
Figure 3.2 EEPROM Access Flow Diagram
The host can disable the EEPROM interface through the GPIO_CFG register. When the interface is
disabled, the EEDIO and ECLK signals can be used as general-purpose outputs, or they may be used
to monitor internal MII signals.
3.10.2.1
Supported EEPROM Operations
The EEPROM controller supports the following EEPROM operations under host control via the
E2P_CMD register. The operations are commonly supported by “93C46” EEPROM devices. A
description and functional timing diagram is provided below for each operation. Please refer to the
E2P_CMD register description in Section 5.3.23, "E2P_CMD – EEPROM Command Register," on
page 95 for E2P_CMD field settings for each command.
ERASE (Erase Location): If erase/write operations are enabled in the EEPROM, this command will
erase the location selected by the EPC Address field (EPC_ADDR). The EPC_TO bit is set if the
EEPROM does not respond within 30ms.
SMSC LAN9215I
Revision 1.5 (07-18-06)
DATA3S1HEET
SMSC [ SMSC CORPORATION ]
