Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
Datasheet
same word is performed, the data read is invalid and should be re-read. This is not a fatal error. The
LAN9215I will reset its read counters and restart a new cycle on the next read.
3.7
3.8
Big and Little Endian Support
TheLAN9215I supports “Big-” or “Little-Endian” processors. To support big-endian processors, the
hardware designer must explicitly invert the layout of the byte lanes.
Word Swap Function
Internally the LAN9215I is 32-bits wide. The LAN9215I supports a Word Swap Function. This feature
is controlled by the Word Swap Register, which is described in Section 5.3.17, "WORD SWAP—Word
Swap Control," on page 90. This register affects how words on the data bus are written to or read from
Controls and Status Registers and the Transmit and Receive Data FIFOs. Refer to Table 3.7, "Word
Swap Control" below for more details. Whenever the LAN9215I transmits data from the Transmit Data
FIFO to the network, the low order word is always transmitted first, and when the LAN9215I receives
data from the network to the Receive Data Fifo, the low-order word is always received first.
Table 3.7 Word Swap Control
BYTE ORDER
D[15:8] D[7:0]
ADDRESS
A1 PIN
DESCRIPTION
Default Mode - Word Swap Register equal to 0x00000000 or any value other than 0xFFFFFFFF
A1 = 0
A1 = 1
Byte 1
Byte 3
Byte 0
Byte 2
When A1=0, the data bus is mapped to the low
order words of CSRs and FIFOs. When A1=1, the
data bus is mapped to the high-order words of
CSRs and FIFOs. Since low-order words are
always transmitted/received first, A1=0 data will
always precede A1=1 data.
Word Swap Mode - Word Swap Register equal to 0xFFFFFFFF
A1 = 0
A1 = 1
Byte 3
Byte 1
Byte 2
Byte 0
When A1=0, the data bus is mapped to the high
order words of CSRs and FIFOs. When A1=1, the
data bus is mapped to the low order words of CSRs
and FIFOs. In this case A1=1 data will always
precede A1=0 data.
3.9
General Purpose Timer (GP Timer)
The General Purpose Timer is a programmable block that can be used to generate periodic host
interrupts. The resolution of this timer is 100uS.
The GP Timer loads the GPT_CNT Register with the value in the GPT_LOAD field and begins counting
down when the TIMER_EN bit is set to a ‘1.’ On a reset, or when the TIMER_EN bit changes from
set ‘1’ to cleared ‘0,’ the GPT_CNT field is initialized to FFFFh. The GPT_CNT register is also initialized
to FFFFh on a reset. Software can write the pre-load value into the GPT_LOAD field at any time; e.g.,
before or after the TIMER_EN bit is asserted. The GPT Enable bit TIMER_EN is located in the
GPT_CFG register.
Once enabled, the GPT counts down either until it reaches 0000h or until a new pre-load value is
written to the GPT_LOAD field. At 0000h, the counter wraps around to FFFFh, asserts the GPT
interrupt status bit and the IRQ signal if the GPT_INT_EN bit is set, and continues counting. The GPT
interrupt status bit is in the INT_STS Register. The GPT_INT hardware interrupt can only be set if the
GPT_INT_EN bit is set. GPT_INT is a sticky bit (R/WC); i.e., once the GPT_INT bit is set, it can only
be cleared by writing a ‘1’ to the bit.
SMSC LAN9215I
Revision 1.5 (07-18-06)
DATA2S9HEET
SMSC [ SMSC CORPORATION ]
