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LAN9211_0711 参数 Datasheet PDF下载

LAN9211_0711图片预览
型号: LAN9211_0711
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能小尺寸单芯片以太网控制器与HP Auto-MDIX的 [High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX]
分类和应用: 控制器以太网
文件页数/大小: 146 页 / 1764 K
品牌: SMSC [ SMSC CORPORATION ]
 浏览型号LAN9211_0711的Datasheet PDF文件第40页浏览型号LAN9211_0711的Datasheet PDF文件第41页浏览型号LAN9211_0711的Datasheet PDF文件第42页浏览型号LAN9211_0711的Datasheet PDF文件第43页浏览型号LAN9211_0711的Datasheet PDF文件第45页浏览型号LAN9211_0711的Datasheet PDF文件第46页浏览型号LAN9211_0711的Datasheet PDF文件第47页浏览型号LAN9211_0711的Datasheet PDF文件第48页  
High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX  
Datasheet  
Note 3.13 The host must only perform read accesses prior to the ready bit being set.  
Once the READY bit is set, the LAN9211 is ready to resume normal operation. At this time the WUPS  
field can be cleared.  
3.10.2.2  
D2 Sleep  
In this state, as shown in Table 3.10, all clocks to the MAC and host bus are disabled and the PHY is  
placed in a reduced power state. To enter this state, the EDPWRDOWN bit in register 17 of the PHY  
(Mode Control/Status register) must be set. This places the PHY in the Energy Detect mode. The  
PM_MODE bits in the PMT_CTRL register must then be set to 10b. Upon setting the PM_MODE bits,  
the LAN9211 will enter the D2 sleep state. The READY bit in PMT_CTRL is cleared when entering the  
D2 state.  
Note 3.14 If carrier is present when this state is entered detection will occur immediately.  
If properly enabled via the ED_EN and PME_EN bits, the LAN9211 will assert the PME hardware  
signal upon detection of a valid carrier. Upon detection, the WUPS field in PMT_CTRL will be set to  
a 01b.  
Note 3.15 The PME interrupt status bit on the INT_STS register (PME_INT) is set regardless of the  
setting of PME_EN.  
A write to the BYTE_TEST register, regardless of whether a carrier was detected, will return the  
LAN9211 to the D0 state and will reset the PM_MODE field to the D0 state. As noted above, the host  
is required to check the READY bit and verify that it is set before attempting any other reads or writes  
of the device. Before the LAN9211 is fully awake from this state the EDPWRDOWN bit in register 17  
of the PHY must be cleared in order to wake the PHY. Do not attempt to clear the EDPWRDOWN bit  
until the READY bit is set. After clearing the EDPWRDOWN bit the LAN9211 is ready to resume normal  
operation. At this time the WUPS field can be cleared.  
Table 3.10 Power Management States  
Device  
BLOCK  
D0  
D1  
(WOL)  
D2  
(NORMAL OPERATION)  
(ENERGY DETECT)  
PHY  
Full ON  
Full ON  
Full ON  
Energy Detect Power-Down  
OFF  
MAC Power  
Management  
RX Power Mgmt. Block  
On  
MAC and Host  
Interface  
Full ON  
Full ON  
OFF  
OFF  
OFF  
Internal Clock  
Full ON  
KEY  
CLOCK ON  
BLOCK DISABLED – CLOCK ON  
FULL OFF  
Revision 1.93 (11-27-07)  
44  
SMSC LAN9211  
DATASHEET