High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
14.5.2.2
Port x MAC Receive Configuration Register (MAC_RX_CFG_x)
Register #:
Port0: 0401h
Port1: 0801h
Port2: 0C01h
Size:
32 bits
This read/write register configures the packet type passing parameters of the port.
BITS
DESCRIPTION
TYPE
DEFAULT
31:8
7
RESERVED
RESERVED
RO
-
R/W
0b
Note:
This bit must always be written as 0.
6
5
RESERVED
RO
-
Enable Receive Own Transmit
R/W
0b
When set, the switch port will receive its own transmission if it is looped back
from the PHY. Normally, this function is only used in Half Duplex PHY
loopback.
4
3
RESERVED
RO
-
Jumbo2K
R/W
0b
When set, the maximum packet size accepted is 2048 bytes. Statistics
boundaries are also adjusted.
2
1
RESERVED
RO
-
Reject MAC Types
R/W
1b
When set, MAC control frames (packets with a type field of 8808h) are
filtered. When cleared, MAC Control frames, other than MAC Control Pause
frames, are sent to the forwarding process. MAC Control Pause frames are
always consumed by the switch.
0
RX Enable
R/W
1b
When set, the receive port is enabled. When cleared, the receive port is
disabled.
Revision 1.2 (04-08-08)
324
SMSC LAN9312
DATASHEET
SMSC [ SMSC CORPORATION ]
