High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
14.4.2.8
Port x PHY Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x)
Index (decimal): 17
Size:
16 bits
This read/write register is used to control and monitor various Port x PHY configuration options.
BITS
DESCRIPTION
TYPE
DEFAULT
15:14
13
RESERVED
RO
-
Energy Detect Power-Down (EDPWRDOWN)
This bit controls the Energy Detect Power-Down mode.
R/W
0b
0: Energy Detect Power-Down is disabled
1: Energy Detect Power-Down is enabled
12:2
1
RESERVED
RO
RO
-
Energy On (ENERGYON)
1b
This bit indicates whether energy is detected on the line. It is cleared if no
valid energy is detected within 256ms. This bit is unaffected by a software
reset and is reset to 1 by a hardware reset.
0: No valid energy detected on the line
1: Energy detected on the line
0
RESERVED
R/W
0b
Revision 1.2 (04-08-08)
300
SMSC LAN9312
DATASHEET
SMSC [ SMSC CORPORATION ]
