High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Chapter 1 Preface
1.1
General Terms
100BT
ADC
ALR
100BASE-T (100Mbps Fast Ethernet, IEEE 802.3u)
Analog-to-Digital Converter
Address Logic Resolution
BLW
BM
Baseline Wander
Buffer Manager - Part of the switch fabric
BPDU
Bridge Protocol Data Unit - Messages which carry the Spanning Tree
Protocol information
Byte
8-bits
CSMA/CD
CSR
Carrier Sense Multiple Access / Collision Detect
Control and Status Registers
Counter
CTR
DA
Destination Address
32-bits
DWORD
EPC
EEPROM Controller
FCS
Frame Check Sequence - The extra checksum characters added to the end
of an Ethernet frame, used for error detection and correction.
FIFO
FSM
GPIO
HBI
First In First Out buffer
Finite State Machine
General Purpose I/O
Host Bus Interface. The physical bus connecting the LAN9312 to the host.
Also referred to as the Host Bus.
HBIC
Host Bus Interface Controller. The hardware module that interfaces the
LAN9312 to the HBI.
Host
External system (Includes processor, application software, etc.)
Internet Group Management Protocol
IGMP
Inbound
Refers to data input to the LAN9312 from the host
Level-Triggered Sticky Bit
This type of status bit is set whenever the condition that it represents is
asserted. The bit remains set until the condition is no longer true, and the
status bit is cleared by writing a zero.
lsb
Least Significant Bit
LSB
MDI
MDIX
Least Significant Byte
Medium Dependant Interface
Media Independent Interface with Crossover
Revision 1.2 (04-08-08)
SMSC LAN9312
DATA1S6HEET
SMSC [ SMSC CORPORATION ]
