FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
TABLE 1 - DESCRIPTION OF PIN FUNCTIONS
144 TQFP
PIN NO.
115-112, Address A[15:1]
110-100
BUFFER
NAME
SYMBOL
DESCRIPTION
TYPE
I
Input. Used by LAN91C110 for internal register
selection.
138
Address AEN
I
I
Input. Used as an address qualifier. Address
decoding is only enabled when AEN is low.
Input. Used during LAN91C110 register accesses
to determine the width of the access and the
register(s) being accessed.
Enable
118, 117
nBE[1:0]
89, 91-95, Data Bus D[15:0]
97-98, 119,
I/O8
Bidirectional. 16-bit data bus used to access the
LAN91C110’s internal registers. Data bus has
weak internal pullups. Supports direct connection
to the system bus without external buffering.
Input. This input is not considered active unless it
is active for at least 100ns to filter narrow glitches.
Open drain output. ARDY may be used when
interfacing asynchronous buses to extend
accesses. Its rising (access completion) edge is
controlled by the XTAL1 clock and, therefore,
asynchronous to the host CPU or bus clock.
Note: Asserted for 100 to 150ns for the
appropriate NO WAIT bit state in the Configuration
register. See the NO WAIT bit description for
complete information.
121-123,
125-128
135
129
Reset
RESET
IS
Asynchro- ARDY
nous
OD16
Ready
120
Local
Device
nLDEV
O16
Output. Local Device. This active low output is
asserted when AEN is low and A4-A15 decode to
the LAN91C110 address programmed into the
high byte of the Base Address Register. nLDEV*
is a combinatorial decode of unlatched address
and AEN signals.
88
nAddress nADS
Strobe
IS
Input. Address strobe. For systems that require
address latching. The rising edge of nADS
indicates the latching moment of A[1:15] and AEN.
All LAN91C110 internal functions of A[1:15] and
AEN are latched.
131
Interrupt INTR0
O4
Output. The interrupt output is enabled by
selecting the appropriate routing bits (INT SEL 1-
0) in the Configuration Register.
132
134
nRead
Strobe
nWrite
Strobe
nRD
IS
IS
Input. Used in asynchronous bus interfaces.
nWR
Input. Used in asynchronous bus interfaces.
56-57, 60- RAM Data RD[31:0]
65, 46-48, Bus
50-54, 35-
I/O4 with
pullups
Bidirectional. Carries the local buffer memory
read and write data. Reads are always 32 bits
wide. Writes are controlled individually at the byte
level.
38, 40-42,
45, 25-28,
30-32, 34
SMSC DS – LAN91C110 REV. B
Page 5
Rev. 09/05/02
SMSC [ SMSC CORPORATION ]
