Non-PCI Single-Chip Full Duplex Ethernet Controller
Chapter 12 Timing Diagrams
A0-15
AEN, nSBHE
nIOCS16
nIORD
VALID ADDRESS
VALID ADDRESS
t4
t15
t20
t6
t3
t5
Z
Z
VALID DATA
OUT
VALID DATA
D0-15
OUT
Parameter
min
typ
units
max
t3
t4
Address, nSBHE, AEN Setup to Control Active
Address, nSBHE, AEN Hold after Control
Inactive
10
20
ns
ns
25
15
12
ns
ns
ns
t5
t6
t15
nIORD Low to Valid Data
nIORD High to Data Floating
A4-A15, AEN Low, BALE High to nIOCS16
Low
t20
Cycle time*
185
ns
BALE Tied High
IOCHRDY not used - t20 has to be met
*Note: The cycle time is defined only for consecutive accesses to the Data Register. These
values assume
that IOCHRDY is not used.
Figure 12.1 – Local Bus Consecutive Read Cycles
Rev. 11/18/2004
Page 92
SMSC DS – LAN91C96I
DATASHEET
SMSC [ SMSC CORPORATION ]
